Cadeira bem organizada, e professor bom com conhecimento da indústria. Slides bons e bem estruturados.

Tópico livre para o projeto, por isso é possível ser original e fazer algo mais interessante que a maior parte dos projetos de cadeiras. Avaliação apenas em projeto com apresentação, e questões após a apresentação. Recomendo ter uma ideia diferente do que usar apenas um filtro, o professor parece ter mais interesse em temas incomuns.

General Thoughts

This course teaches you how to work with SoC/FPGA systems allowing you to mix hardware and software in order to have a good balance of better performance while not investing much time in creating such a system.
It also teaches a tool called HLS, where you could write C++ code with some macros and it would create a Verilog description of the hardware. This is a new tool so it is prone to some bugs and some figuring out both by the students and the professor, which you could feel throughout the course.
Overall I liked this course but I can see why some people might...

Poorly organized

Confusing and poorly planned classes, software with little support and outdated tutorials. You don't go to learn, you go to be assessed.

Poorly organized course, the professor does not know the Labs properly neither does he prepare the classes or structure it. The tool learned is not used in the industry either. Do not recommend it.